Various methods of identifying failure locations on an LSI (Large Scale Integration) chip already exist. For example, as disclosed in Patent Document 1, there is the logical failure analysis method which uses an EB (Electron Beam) tester on suspected failure locations on the surface of an LSI chip, and identifies the failure locations. Further, there is the leak failure analysis method which uses a device such as an emission microscope to monitor faint luminescent states on the LSI chip surface and identifies the failure locations.
On the other hand, when identifying failure locations on a type of LSI chip which is mounted by a flip chip, the LSI chip is mounted on a board wherein a monitoring hole (monitoring window) has been opened up (hereinafter “evaluation board”). The board is mounted into an analysis apparatus, and then the failure locations are identified via the monitoring window. In addition to the monitoring window, this evaluation board has power supply bumps (BUMP) for providing power to the LSI chip, ground bumps for providing ground to the LSI chip, and signal bumps for providing “Low” and “High” electrical signals to the LSI chip.
Recent LSI chips have increasingly high performance and consume much power. So when an LSI chip is mounted on an evaluation board having a large monitoring window and failure locations are identified, the power supply bump area has become narrower, and making it impossible to provide sufficient power to the LSI chip. Therefore, the size of the monitoring window on the evaluation board is kept to a minimum, multiple types of evaluation boards having monitoring windows in different areas are being manufactured, and failure locations are being identified using evaluation boards which have monitoring windows corresponding to the suspected failure locations on the LSI chip from each evaluation board.
[Patent Document 1] Japanese Unexamined Patent Application Publication No. H11-111759
However, as mentioned above, multiple types of evaluation boards having monitoring windows in different positions are necessary to be able to monitor an entire LSI chip with an analysis apparatus. So there was a problem in which the cost of manufacturing evaluation boards became very high.
In other words, being able to analyze the failure locations across an entire LSI chip without manufacturing multiple types of evaluation boards even if the size of the monitoring windows is restricted, and reducing the manufacturing cost of evaluation boards is of paramount importance.
An object of the present disclosure, which was created to solve the above-mentioned problems with the prior art, is to provide an evaluation board which can reduce manufacturing costs and a failure location detection method which uses such a board.